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SPCE061A
16-bit Sound Controller with 32K x 16 Flash Memory
Preliminary
AUG. 02, 2002 Version 0.1
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. No responsibility is assumed by In addition, SUNPLUS products Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product
Preliminary
SPCE061A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 4 2. BLOCK DIAGRAM ...................................................................................................................................................................................... 4 3. FEATURES.................................................................................................................................................................................................. 4 4. APPLICATION FIELD ................................................................................................................................................................................. 4 5. SIGNAL DESCRIPTIONS ........................................................................................................................................................................... 5 FUNCTIONAL DESCRIPTIONS ....................................................................................................................................................................... 7 5.1. CPU ..................................................................................................................................................................................................... 7 5.2. MEMORY ............................................................................................................................................................................................... 7 5.3. PLL, CLOCK, POWER MODE .................................................................................................................................................................. 7 5.4. POWER SAVINGS MODE ......................................................................................................................................................................... 7 5.5. LOW VOLTAGE DETECTION AND LOW VOLTAGE RESET............................................................................................................................. 8 5.6. INTERRUPT ............................................................................................................................................................................................ 8 5.7. I/O ........................................................................................................................................................................................................ 8 5.8. TIMER/COUNTER ................................................................................................................................................................................... 9 5.9. SLEEP, WAKEUP AND WATCHDOG ......................................................................................................................................................... 10 5.10. ADC (ANALOG TO DIGITAL CONVERTER) / DAC................................................................................................................................. 10 5.11. SERIAL INTERFACE I/O (SIO)............................................................................................................................................................. 10 5.12. UART ...............................................................................................................................................................................................11 5.13. AUDIO ALGORITHM.............................................................................................................................................................................11 5.14. BONDING OPTION SUMMARY ..............................................................................................................................................................11 5.15. IDE TOOLS FUNCTION .......................................................................................................................................................................11 5.16. SECURITY FUNCTION .........................................................................................................................................................................11 6. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 12 6.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 12 6.2. DC CHARACTERISTICS (VDD = 3.3V, VDDIO = 5.5V (PORTA & B), TA = 25) ..................................................................................... 12 6.3. DC CHARACTERISTICS (VDD = 3.3V, VDDIO = 3.3V (PORTA & B), TA = 25)................................................................................... 12
6.4. DC CHARACTERISTICS (VDD = 2.7V, VDDIO = 2.7V (PORTA & B) , TA = 25) .................................................................................... 13 6.5. DC CHARACTERISTICS (VDD = 2.4V, VDDIO = 2.4V (PORTA & B) ,TA = 25) ..................................................................................... 13 6.6. ADC CHARACTERISTICS (VDD = 3.3V, TA = 25) ............................................................................................................................... 14 6.7. DAC CHARACTERISTICS (VDD = 3.3V, TA = 25) ............................................................................................................................... 14 6.8. PULL HIGH RESISTER AND VDDIO ......................................................................................................................................................... 14 6.9. I/O OUTPUT HIGH CURRENT IOH AND VOH .............................................................................................................................................. 14 6.10. PULL LOW RESISTER AND VDDIO......................................................................................................................................................... 15 6.11. I/O OUTPUT LOW CURRENT IOL AND VOL .............................................................................................................................................. 15 7. APPLICATION CIRCUITS......................................................................................................................................................................... 16 7.1. APPLICATION CIRCUIT - (1)................................................................................................................................................................... 16 7.2. APPLICATION CIRCUIT - (2)................................................................................................................................................................... 17 7.3. APPLICATION CIRCUIT - (3)................................................................................................................................................................... 18 7.4. APPLICATION CIRCUIT - (4)................................................................................................................................................................... 19 7.5. APPLICATION CIRCUIT - (5)................................................................................................................................................................... 20 7.6. APPLICATION CIRCUIT - (6)................................................................................................................................................................... 21
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SPCE061A
8. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 22 8.1. PAD ASSIGNMENT ............................................................................................................................................................................... 22 8.2. ORDERING INFORMATION ..................................................................................................................................................................... 22 8.3. PAD LOCATIONS.................................................................................................................................................................................. 23 9. DISCLAIMER............................................................................................................................................................................................. 24 10. REVISION HISTORY ................................................................................................................................................................................. 25
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Preliminary
SPCE061A
16-BIT SOUND CONTROLLER WITH 32K X 16 FLASH MEMORY
1. GENERAL DESCRIPTION
The SPCE061A, a 16-bit architecture product, carries the newest 16-bit microprocessor, 'nSPTM (pronounced as micro-n-SP), developed by SUNPLUS Technology. signal processes easily and rapidly. recognition. This high processing speed assures the 'nSPTM is capable of handling complex digital Therefore, the SPCE061A is applicable to the areas of digital sound process and voice The operating voltage of 2.4V through 3.6V and The memory capacity speed of 0.32MHz through 49.152MHz yield the SPCE061A to be easily used in varieties of applications. includes 32K-word flash memory plus a 2K-word working SRAM. Other features include 32 programmable multi-functional I/Os, two 16-bit timers/counters, 32768Hz Real Time Clock, Low Voltage Reset/Detection, eight channels 10-bit ADC (one channel built-in MIC amplifier with auto gain controller), 10-bit DAC output and many others.
3. FEATURES
! 16-bit 'nSPTM microprocessor ! CPU clock: 0.32MHz - 49.152MHz ! Operating voltage: 2.4V - 3.6V ! Program Flash Operating voltage: 2.7V - 3.6V ! IO PortA & B operating voltage: 2.4V - 5.5V ! 32K-word flash memory ! 2K-word working SRAM ! Software-based audio processing ! Crystal Resonator ! Standby mode (Clock Stop mode) for power savings, Max. 2.0A @ VDD = 3.3V ! Two 16-bit timers/counters ! Two 10-bit DAC outputs ! 32 general I/Os (bit programmable) ! 14 INT sources with two priority levels ! Key wakeup function (IOA0 - 7) ! PLL feature for system clock
2. BLOCK DIAGRAM
16-bit u'nSP and ICE controller 16-bit Timer/Counter x2 TimerBase INT control VMIC VEXTREF VADREF AGC MICOUT MICP MICN OPI AUD1 AUD2
! 32768Hz Real Time Clock (RTC) ! Eight channels 10-bit AD converter ! ADC external top reference voltage ! 2.0V voltage regulator output, 5mA of driving capability ! Serial interface I/O (SIO) ! Built-in microphone amplifier and AGC function ! UART receiver and transmitter (full duplex) ! Low voltage reset and low voltage detection ! Watchdog enable (bonding option) ! ICE function for development and down load into flash memory
IOB0 (SCK)
ICE ICECLK ICESDA SLEEP RESET VCOIN X32I X32O
FLASH
RAM
PLL
CPU Clock RTC
10-bit A/D & AGC
LVD/LVR WATCHDOG UART
IOB7 (Rx) IOB10 (Tx) IOB1 (SDA)
10-bit DAC1 Output 10-bit DAC2 Output SIO
! Security function to protect code to be read and written.
32 PIN GENERAL I/O PORT
IOA15 - 0
IOB15 - 0
4. APPLICATION FIELD
! Voice recognition products ! Intelligent interactive talking toys ! Advanced educational toys ! Kids learning products ! Kids storybook ! General speech synthesizer ! Long duration audio products ! Recording / playback products
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5. SIGNAL DESCRIPTIONS
Mnemonic IOA [15:8] IOA [7:0] IOB [15:11] IOB 10 IOB 9 IOB 8 IOB 7 IOB 6 IOB 5 IOB 4 IOB 3 IOB 2 IOB 1 IOB 0 DAC1 DAC2 X32I X32O VCOIN AGC MICN MICP V2VREF MICOUT OPI VEXTREF VMIC VADREF VDD VSS VDDIO VSSIO AVDD AVSS PIN No. 46 - 39 34 - 27 50 - 54 57 58 59 60 61 62 63 64 65 66 67 12 13 2 1 70 16 19 21 14 18 17 23 25 22 5, 69 10, 26, 71 37, 38, 56 35, 36, 48 24 15 68 49 7 8 9 3 47 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I O I I I I O O I I O O I I I I I I I O I I I/O I I IOA [15:8]: bi-directional I/O ports IOA [7:0] can be software programmed to wakeup I/O pins IOA [6:0] can be optioned as ADC Line-in input IOB [15:11]: bi-directional I/O ports IOB10 can also be selected as UART Transmitter (Tx). IOB9 can also be Multi-duty cycle output of TimerB (BPWMO). IOB8 can also be Multi-duty cycle output of TimerA (APWMO). IOB7 can also be selected as UART receiver (Rx). IOB6 is a bi-directional I/O ports. IOB5 can also be selected as feedback signal with EXT2. IOB4 can also be selected as feedback signal with EXT1. IOB3 can also be selected as an external interrupt input pin (EXT2)(Negative-edge Triggered). IOB2 can also be selected as an external interrupt input pin (EXT1)(Negative-edge Triggered). IOB1 can also be selected as a serial interface data. (SDA) IOB0 can also be selected as a serial interface clock (SCK) Audio DAC1 output Audio DAC2 output Oscillator Crystal input Oscillator Crystal output RC filter connection for PLL AGC control pin Microphone differential input (negative) Microphone differential input (positive) 2.0V output voltage, 5.0mA of driving capability (can be used as external ADC Line_IN top reference voltage) Microphone 1 amplifier output Microphone 2 amplifier input ADC Line_IN top external reference voltage input pin Microphone power supply AD reference voltage (generated by internal AD converter). Positive supply for logic Ground reference for logic and I/O pins Positive supply for I/O pins Ground reference for I/O pins Positive supply for analog circuit including ADC, DAC and 2.0V regulator Ground reference for analog circuit including ADC, DAC and 2.0V regulator An active low reset to the chip Sleep mode (active high) ICE enable (active high) ICE serial interface clock ICE serial interface data Connected to high for test mode, normally connected to GND (test mode disabled) or unconnected. ROMT Flash memory test, normally unconnected. 5 AUG. 02, 2002 Preliminary Version: 0.1
nd st
Description
RESET
SLEEP ICE ICECLK ICESDA TEST
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SPCE061A
Mnemonic N/C WDGOPT* PFUSE, PVIN PIN No. 4, 55 6 20, 11 Type I I I Not used. Connected to high for watchdog disabled, unconnected for watchdog enabled. Security enable using fuse.
VDD
Description
Note*: WDGOPT is the watchdog option pin, selected by bonding option. Remain WDGOPT float (unconnected to VDD) to enable the watchdog. In contrast, connecting WDGOPT to VDD will disable watchdog. The reason of placing WDTOPT adjacent to VDD is to facilitate connection between VDD and WDGOPT when disabling watchdog is necessary.
WDGOPT
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SPCE061A
FUNCTIONAL DESCRIPTIONS
5.1. CPU
The SPCE061A is equipped with a 16-bit 'nSPTM, the newest 16-bit microprocessor by SUNPLUS and pronounced as micro-n-SP. Eight registers are involved in 'nSPTM: R1 - R4 Moreover, a high performance hardware multiplier with the capability of FIR filter is also built in to reduce the software multiplication loading.
(General-purpose registers), PC (Program Counter), SP (Stack Pointer), Base Pointer (BP) and SR (Segment Register). The interrupts include three FIQs (Fast Interrupt Request) and eight IRQs (Interrupt Request), plus one software-interrupt, BREAK.
5.2. Memory 5.2.1. SRAM
The amount of SRAM is 2K-word (including Stack), ranged from $0000 through $07FF with access speed of two CPU clock cycles.
Phase Lock Loop 32768Hz X'tal (PLL) System Clock generator
FOSC
PLL OUT 24.576MHz(default) 20.48MHz 32.768MHz 40.96MHz 49.152MHz
Fosc/n n:1,2,4,8,16,32,64
CPU Clock
(Default : Fosc/8)
b7
b6
b5
b2 b1 b0 of P_SystemClock(W )($7013H) CPU clock frequency selection
b7,b6,b5 of P_SystemClock(W )($7013H) System clock frequency selection
5.2.2. Flash memory
Flash memory ($008000 ~ $00FFFF) is a high-speed memory with access speed of two CPU clock cycles. FLASH erase and program functions must be used in IDE tools. wake CPU up whenever RTC occurs. of RTC occurrence. Since the RTC is generated each 0.5 seconds, time can be traced by the numbers In addition, SPCE061A supports 32768Hz In strong mode, In oscillator in strong mode and auto_weak mode.
5.3. PLL, Clock, Power Mode 5.3.1. PLL (Phase Lock Loop)
The purpose of PLL is to provide a base frequency (32768Hz) and to pump the frequency from 20.48MHz to 49.152MHz for system clock (Fosc). The default PLL frequency is 24.576MHz.
32768Hz OSC always runs at the highest power consumption.
auto_weak mode, however, it runs in strong mode for the first 7.5 seconds and changes back to auto_weak mode automatically to save powers.
5.4. Power Savings Mode 5.3.1.1. System clock
Basically, the system clock is provided by PLL and programmed by the Port_SystemClock (W) to determine the frequency of clock for system. The default system clock Fosc = 24.576MHz and The initial CPU clock is This avoids CPU clock is Fosc/8 if not specified. The SPCE061A also offers a power savings mode (standby mode) for low power application needs. To enter standby mode, the desired key wakeup port(IOA[7:0]) must be configured to input first. And read the Port_IOA_Latch(R) to latch the IOA state before entering the standby mode. Also remember to enable the After that, stop the In such mode, corresponding interrupt source(s) for wakeup.
Fosc/8 after system wakes up and to be adjusted to desired CPU clock by programming the Port_SystemClock (W). Flash ROM reading failure when system wakes up.
CPU clock by writing the STOP CLOCK Register (b0~b2 of Port_SystemClock (W)) to enter standby mode. awoken. SRAM and I/Os remain in the previous states till CPU being
5.3.1.2. 32768Hz RTC
The Real Time Clock (RTC) is normally used in watch, clock or other time related products. loaded in SPCE061A. A 2Hz-RTC (1/2 second) function is The RTC counts the timing as well as to 7
The wakeup sources in SPCE061A include Port IOA7 After SPCE061A is awoken, the CPU will Programmer can also enable
0 and IRQ1 - IRQ6.
continue to execute the program.
or disable the 32768Hz OSC when CPU is in standby mode. AUG. 02, 2002 Preliminary Version: 0.1
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5.5. Low Voltage Detection and Low Voltage Reset 5.5.1. Low Voltage Detection (LVD)
The Low Voltage Detection (LVD) reports the circumstance of present voltage. 2.8V, and 3.2V. Port_LVD_Ctrl (W). 2.8V. There are four LVD levels to be selected: 2.4V, These levels can be programmed via As an example, suppose LVD is given to In such state, program can be Interrupt Source Fosc/1024 Timer A Timer B EXT2 EXT1 Key change wakeup 4096Hz 2048Hz 1024Hz 4Hz 2Hz Time-base 1 Time-base 2 UART (TxRDY or RxRDY) With the LVR function, a Without Interrupt Name FIQ_PWM/IRQ0_PWM FIQ_TMA/ IRQ1_TMA FIQ_TMB/ IRQ2_TMB IRQ3_EXT2 IRQ3_EXT1 IRQ3_KEY IRQ4_4KHz IRQ4_2KHZ IRQ4_1KHz IRQ5_4Hz IRQ5_2Hz IRQ6_TMB1 IRQ6_TMB2 UART IRQ Priority High(FIQ) High(FIQ) High(FIQ) Low Low Low Low Low Low Low Low Low Low Low
When the voltage drops below 2.8V, the b15 of
Port_LVD_Ctrl is read as HIGH. designed to react to this condition.
5.5.2. Low voltage reset
In addition to the LVD, the SPCE061A has another important function, Low Voltage Reset (LVR). reset signal is generated to reset system when the operating voltage drops below 2.2V for 4 consecutive clock cycles. operating voltage drops below 2.2V. drops below 2.2V. LVR, the CPU becomes unstable and malfunction when the The LVR will reset all functions to the initial operational (stable) states when the voltage A LVR timing diagram is given as follows:
5.7. I/O
Two I/O ports are built in SPCE061A, PortA and PortB. PortA is an ordinary I/O with programmable wakeup capability. The In
Fosc VDD 2.2V Tw
addition to the regular IO function, the PortB can also perform some special functions in certain pins. operates from 3.6V (VDD) to 5.5V. diagram is an I/O schematic.
Treset
Suppose operating
voltage is running at 3.6V (VDD) and VDDIO (power for I/O) In such condition, the I/O pad The following is capable of operating from 0V through VDDIO.
Tvdd
RESET Tw=Fosc x 4 cycle Tvdd > Tw Treset = Fosc x512 cycle
Buffer(R) Port_Data(W)
5.6. Interrupt
The SPCE061A has 14 interrupt sources, grouped into two types, FIQ (Fast Interrupt Request) and IRQ (Interrupt request). priority of FIQ is higher than IRQ. while IRQ is the low-priority one. FIQ, but not by another IRQ. other interrupt sources. The FIQ is the high-priority interrupt An IRQ can be interrupted by a
Register Port_Buffer(W) Port_DIR(R/W) Port_ATTR(R/W) Control logic
pull high Pin pad
pull low
A FIQ cannot be interrupted by any
Data(R)
Although data can be written into the same register through Port_Data and Port_Buffer, they can be read from different places, Buffer (R) and Data (R). The IOA [7:0] is the key wakeup port. Wakeup is triggered when In addition to A To activate key wakeup function, latch data on PORT_IOA_Latch and enable the key wakeup function. the PortA state is different from at the time latched.
an ordinary I/O port, PortB carries some special functions. summary of PortB special functions is listed as follows:
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Special function in PortB PortB IOB0 IOB1 IOB2 Special Function SCK SDA EXT1 Feedback Output1 IOB3 EXT2 Feedback Output2 IOB4 IOB5 IOB7 IOB8 IOB9 IOB10 Feedback Input1 Feedback Input2 Rx APWMO BPWMO Tx UART Receiver TimerA PWM output TimerB PWM output UART Transmitter Refer to see UART section Refer to Timer/Counter section Refer to Timer/Counter section Refer to UART section Function Description Serial interface clock Serial interface data External interrupt source 1(Negative-edge Triggered) Works with IOB4 by adding a RC circuit between them to get an OSC to EXT1 interrupt External interrupt source 2(Negative-edge Triggered) Works with IOB5 by adding a RC circuit between them to get an OSC to EXT2 interrupt IOB3 set as input mode IOB3 set as inverted output Note Refer to see SIO section Refer to see SIO section IOB2 set as input mode IOB2 set as inverted output
Default state: Pull Low PWM: Pulse Width Modulation
Refer to the above table, the configuration of IOB2, IOB3, IOB4, and IOB5 involves feedback function in which an OSC frequency can be obtained from EXT1 (EXT2) by simply adding a RC circuit between IOB2 (IOB3) and IOB4 (IOB5).
Initially, write a value of N into a timer and select a desired clock source, timer will start counting from N, N+1, N+2, ... through FFFF. An INT (TimerA/TimerB) signal is generated at the next At the same time, N will be The clock source A is clock after reaching "FFFF" and the INT signal is transmitted to INT controller for further processing. reloaded into timer and start all over again. source. gating.
5.8. Timer/Counter
The SPCE061A provides two 16-bit timers/counters, TimerA and TimerB. The TimerA is called a universal counter. TimerB is a In general-purpose counter. The clock source of TimerA comes When timer
a high frequency source and clock source B is a low frequency The combination of clock source A and B provides a A "1" represents pass signal and not The EXT1 Moreover, counter can In contrast, "0" indicates deactivating timer. variety of speeds to TimerA.
from the combination of clock source A and clock source B. TimerB, the clock source is given from source C. signal. Clock of Source A Fosc/2 Fosc/256 32768Hz 8192Hz 4096Hz 1 0 EXT1 Clock of Source B 2048Hz 1024Hz 256Hz TMB1 4Hz 2Hz 1 EXT2
and EXT2 are the external clock sources. levels) PWM pulse width counter.
overflows, an INT signal is sent to CPU to generate a time-out
generate time-out signal for input clock source to a four bits (16 A variety of clock duration can be generated and exported from IOB8 (APWMO) and IOB9 (BPWMO). The following example is a 3/16-duration cycle. waveform is made by selecting a pulse Port_TimerA_Ctrl (W) [9:6]. The APWMO width through
Clock of Source C Fosc/2 Fosc/256 32768Hz 8192Hz 4096Hz 1 0 EXT1
As a result, each 16 cycles will These PWM
generate a pulse width defined in control port. devices.
signals can be applied for controlling the speed of motor or other
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TimerA_Timeout Tapwmo Tduty APWMO
Generally speaking, the clock source A and C are fast clock sources and source B comes from RTC system (32768Hz). Therefore, clock source B can be utilized as a precise counter for time counting, e.g., the 2Hz clock can be used for real time counting.
5.9.2. Watchdog
The purpose of watchdog is to monitor if the system operates normally. Within a certain period, watchdog must be cleared. If watchdog is not cleared, CPU assumes the program has been running in an abnormal condition. over again. option. be reset. As a result, the CPU will reset the system to the initial state and start running the program all
5.8.1. Timebase
Timebase, generated by 32768Hz, is a combination of frequency selections. and TMB2. The outputs of timebase block are named to TMB1 TMB1 is frequency for TimerA (Clock source B).
The watchdog function can be removed by bonding If
In SPCE061A, the clear period is 0.75 seconds.
watchdog is cleared within each 0.75 seconds, the system will not To clear watchdog, simply write "0bxxxx xxxx xxxx The content written to xx01" to Port_Watchdog_Clear(W).
The TMB1 and TMB2 are the sources for Interrupt (IRQ6). Furthermore, timebases generates additional 2Hz to 4096Hz interrupt sources (IRQ4 and IRQ5) for Real-Time-Clock (RTC).
Port_Watchdog_Clear (W) for watchdog clearance must be exactly the same as the one illustrated above (0bxxxx xxxx xxxx xx01). Other values given to the Port_Watchdog_Clear (W) for The watchdog clearance may end up with system reset. 32768Hz is turned on.
TMB2 128Hz 256Hz 512Hz 1024Hz Default: 128Hz
TMB1 8Hz 16Hz 32Hz 64Hz Default: 8Hz
watchdog function remains enabled during standby mode if the
5.10. ADC (Analog to Digital Converter) / DAC
The SPCE061A has eight channels 10-bit ADC (Analog to Digital Converter). The function of an ADC is to convert analog signal to The eight digital signal, e.g. a voltage level into a digital word.
5.9. Sleep, Wakeup and Watchdog 5.9.1. Wakeup and sleep
1) Sleep: After power-on reset, IC starts running until a sleep command occurs. When a sleep command is After accepted, IC will turn the system clock (PLL) off. all, it enters sleep mode. 2) Wakeup: CPU waking up from sleep mode requires a wakeup signal to turn the system clock (PLL) on. The IRQ signal makes CPU to complete the wakeup process and initialization. The key wakeup and interrupt sources (IRQ1 - IRQ6) can be used for wakeup sources.
channels of ADC can be seven channels of line-in from IOA [6:0] or one channel microphone (MIC) input through amplifier and AGC controller. The MIC amplifier circuit is capable of reducing Moreover, an external resistor can be The ADC common mode noise by transmitting signals through differential MIC Inputs (MICN, MICP). applied to adjust microphone gain and time of AGC operating. The AD needs to select source of line-in before conversion. is able to choose the external or internal (=AVDD) top reference voltage. If constant voltage source is unavailable, SPCE061A offers a constant voltage 2.0V with 5.0mA driving ability with a capacitor connected. The SPCE061A has two 10-bit D/A with 2.0mA or 3.0mA driving current for audio outputs, DAC1 and DAC2.
5.11. Serial interface I/O (SIO)
Serial interface I/O offers a one-bit serial interface for communication. This serial interface is capable of transmitting or
receiving data via two I/O pins, IOB0 (SCK) and IOB1 (SDA). (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 10 AUG. 02, 2002 Preliminary Version: 0.1
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WRITE MODE
SCK SDA
Ax+1 Ax Ax-1 A0 Dx+1 Dx D0 Dx+1 Dx D0
write control bit=0
SDA
1st write P_SIO_Data (W), $701AH
STOP 2nd write P_SIO_Data (W), $701AH
READ MODE
read control bit = 1 SCK SDA
SDA
Ax+1 Ax Ax-1 A0 Dx+1 Dx D0 Dx+1 Dx D0
1st Read P_SIO_Data (R), $701AH
STOP 2nd Read P_SIO_DAta (R), $701AH
5.12. UART
UART block provides a full-duplex standard interface that facilitates the communication with other devices. maximum baud-rate can be up to 115200bps. With this The The interface, SPCE can transmit and receive simultaneously. be accomplished by using PortB and Interrupt (UART IRQ). Rx and Tx of UART are shared with IOB7 and IOB10. When SPCE061A receives and/or transmits a frame of data, the b7 (RxRDY) and/or b6 (TxRDY) in Port_UART_Command2(R) will be set to "1" and the UART IRQ is activated at the same time.
This function can
start bit
D0
D1
D2
D3
D4
D5
D6
D7
parity bit
stop bit
1-bit Start
8-bit data
can be enabled/disable; also even/odd check
1-bit Stop
5.13. Audio Algorithm
The following speech types can be used in SPCE061A: PCM, LOG PCM, SACM_A3200, SACM_S720, SACM_S240, SACM_S480, For melody SACM_S530, SACM_A1600, SACM_A2000 ,
5.15. IDE Tools Function
The functions of IDE include the follows: 1). C compiler or Assembly and Link. 2). Download program into FLASH 3). Single step trace 4). Break point (break point for debugging) 5). Run (execute)
and SACM_A2000_DVR (Digital Voice Recorder). SACM_MS02 (wave-table) synthesizers.
synthesis, the SPCE061A supports SACM_MS01 (FM) and
5.14. Bonding Option Summary
The SPCE061A has the following bonding options: 1). Watchdog function
5.16. Security Function
Security function is able to protect code to be read or written. When program is downloaded into flash memory, program can be read/written protection from IDE tools for security purpose. Burn
SPCE061A
X32I X32O
fuse to disable IDE function, where PFUSE supplies 5.0V and PVIN connects to ground (0V) about one second. After all, the flash memory can no longer be read or written.
20 pf
20 pf
(a) Crystal or Ceramic Resonator Connections
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6. ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics DC Supply Voltage PortA/B Pad Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
conditions see DC Electrical Characteristics.
Symbol V+ VIO VIN TA TSTO
Ratings < 4.0V < 7.0V -0.5V to V+ + 0.5V 0 to +60 -50 to +150
For normal operational
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device.
6.2. DC Characteristics (VDD = 3.3V, VDDIO = 5.5V (PortA & B), TA = 25)
Characteristics Operating Voltage Operating Current Standby Current Input High Level Input Low Level Output DAC current (AUD1, AUD2) Output High Current Output Low Current Input Pull-Low Resister (PA15 :0, PB15 :0) Input Pull-High Resister (PA15 :0, PB15 :0) Symbol VDD IOP ISTB VIH VIL IAUD IOH IOL RPL RPH Limit Min. 2.4 Typ. 3.3 26 0.7VDDIO 0.3VDDIO -2.0 -3.0 -5.0 12 110 150 Max. 3.6 2.0 Unit V mA A V V mA mA mA K K 2.0mA mode 3.0mA mode VOH = 4.0V VOL = 1.0V VIN = VDDIO VIN = VSS For one channel DAC FOSC = 49.152MHz, AD, DAC disable, no loading Disable 32KHz crystal Test Condition
6.3. DC Characteristics (VDD = 3.3V, VDDIO = 3.3V (PortA & B), TA = 25)
Characteristics Operating Voltage Operating Current Standby Current Input High Level Input Low Level Output DAC current (AUD1, AUD2) Output High Current Output Low Current Input Pull-Low Resister (PA15 :0, PB15 :0) Input Pull-High Resister (PA15 :0, PB15 :0) (c) Sunplus Technology Co., Ltd. Proprietary & Confidential Symbol VDD IOP ISTB VIH VIL IAUD IOH IOL RPL RPH Limit Min. 2.4 Typ. 3.3 26 0.7VDDIO 0.3VDDIO -2.0 -3.0 -2.9 6.7 175 242 12 Max. 3.6 2.0 Unit V mA A V V mA mA mA K K 2.0mA mode 3.0mA mode VOH = 2.6V VOL = 0.7V VIN = VDDIO VIN = VSS AUG. 02, 2002 Preliminary Version: 0.1 For one channel DAC FOSC = 49.152MHz, AD, DAC disable, no loading Disable 32KHz crystal Test Condition
Preliminary
SPCE061A
6.4. DC Characteristics (VDD = 2.7V, VDDIO = 2.7V (PortA & B) , TA = 25)
Characteristics Operating Voltage Operating Current Standby Current Input High Level Input Low Level Output DAC current (AUD1, AUD2) Output High Current Output Low Current Input Pull-Low Resister (PA15 :0, PB15 :0) Input Pull-High Resister (PA15 :0, PB15 :0) Symbol VDD IOP ISTB VIH VIL IAUD IOH IOL RPL RPH Limit Min. 2.4 Typ. 2.7 17 0.7VDDIO 0.3VDDIO -2.0 -3.0 -1.9 4.4 230 325 Max. 3.6 2.0 Unit V mA A V V mA mA mA K K 2mA mode 3mA mode VOH = 2.1V VOL = 0.5V VIN = VDDIO VIN = VSS For one channel DAC FOSC = 49.152MHz, AD, DAC disable, no loading Disable 32KHz crystal Test Condition
6.5. DC Characteristics (VDD = 2.4V, VDDIO = 2.4V (PortA & B) ,TA = 25)
Characteristics Operating Voltage Operating Current Standby Current Input High Level Input Low Level Output DAC current (AUD1, AUD2) Output High Current Output Low Current Input Pull-Low Resister (PA15 :0, PB15 :0) Input Pull-High Resister (PA15 :0, PB15 :0) Symbol VDD IOP ISTB VIH VIL IAUD IOH IOL RPL RPH Limit Min. 2.4 Typ. 2.4 14 0.7VDDIO 0.3VDDIO -2.0 -3.0 -1.5 3.5 275 395 Max. 3.6 2.0 Unit V mA A V V mA mA mA K K 2.0mA mode 3.0mA mode VOH = 1.92V VOL = 0.48V VIN = VDDIO VIN = VSS For one channel DAC FOSC = 49.152MHz, AD, DAC disable, no loading Disable 32KHz crystal Test Condition
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AUG. 02, 2002 Preliminary Version: 0.1
Preliminary
SPCE061A
6.6. ADC Characteristics (VDD = 3.3V, TA = 25)
Characteristics ADC Power Dissipation for LINE_IN ADC Power Dissipation For MIC_IN ADC LINE_IN Input Voltage Range from IOA[6:0] ADC Microphone Input Voltage Range External ADC Top Voltage Resolution of ADC Signal-to-Noise Plus Distortion of ADC from Line In Effective Number of Bit Integral Non-Linearity of ADC Differential Non-Linearity of ADC AD Conversion Rate Microphone Amplifier Gain (Note 7)
without causing damages to the devices. Note2: The ADC performance is limited by the system noise level and therefore, the SPCE061A only guarantees to the 8-bit accuracy when VEXTREF is 2.0V. Note3: The LSB means Least Significant Bit. VINL = 2.0V, 1LSB = 2.0V/2^10 = 1.953mV. Note4: The SINAD testing condition at VINLp-p = 0.8*VDD, FCONV = Fcpu/512 = 49MHz/512 = 95KHz, Fin=1.0KHz Sine waves at VDD = 3.0V from the IOA [6:0] input. Note5: ENOB = (SINAD-1.76)/6.02. Note6: The ADC of SPCE061A guarantees no data missed during conversion. Note7: The microphone amplifier maximum gain = 15 * (60K/(1.5K+REXT) V/V. The REXT is external resistor between OPI and MICOUT. The gain is 132V/V (=42dB) when REXT is 5.1K.
Symbol IADC
Unit Min. Typ. 1.0 1.9 56 9.0 4.0 0.5 Max. VDD+0.3 VDD+0.3 VDD+0.3 10 Fcpu/512 42
Unit mA mA V V V bits dB bits LSB (Note 3) LSB Hz dB
VINL (Note 1) VINM VEXTREF (Note 2) RESO SINAD (Note 4) ENOB (Note 5) INL DNL (Note 6) FCONV A MIC
VSS-0.3 VSS-0.3 2.0 8.0 -
Note1: Internal protection diodes clamp the analog input to VDD and VSS. These diodes allow the analog input to swing from (VSS-0.3V) to (VDD+0.3V)
6.7. DAC Characteristics (VDD = 3.3V, TA = 25)
Characteristics DAC resolution Signal to Noise Ratio of DAC Sample Rate Symbol RESO SNR FS Unit Min. 54 Typ. Max. 10 100K Unit bit dB Hz
6.8. Pull High Resister and VDDIO
500 RPH(Kohms) 400 300 200 100 0 2.4 3.4 VDDIO(V) 4.4
6.9. I/O Output High Current IOH and VOH
15 IOH (mA) 10 5 0 0.5 1.5 2.5 VOH (V) 3.5 4.5
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AUG. 02, 2002 Preliminary Version: 0.1
Preliminary
SPCE061A
6.10. Pull Low Resister and VDDIO
300 250 200 150 100 50 0 2.4
6.11. I/O Output Low Current IOL and VOL
25 20
RPL(Kohms)
IOL(mA)
15 10 5 0 0.5
2.9
3.4
3.9
4.4
4.9
1.5
2.5 V OL(V)
3.5
4.5
VDDIO(V)
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AUG. 02, 2002 Preliminary Version: 0.1
Preliminary
AUG. 02, 2002
3300p 3.3K 0.1 1K 3K 0.22 0.22 MIC 3K
10K 10K
SPCE061A
32768Hz
VDD
20p
20p
4.7K VDDH(5V) RESET 87 100 0.1 0.1 RESET X32O X32I
VCOIN
0.22 Speaker1 3 1K MICP 0.1 VDDH(5V) SPY0030A 87 100 0.1 MICN 6 1K 4 0.1 1 2 DAC1 5 VMIC
220
0.22 Speaker2 3 6 0.1 4 1K 1 2 5 0.1 DAC2 1K MICOUT 0.22
SPCE061A
5.1K OPI
5000p
SPY0030A IOA[15:7] IOA[15:7] AGC IOB[15:0] VDDH(5V) VDDIO 100 0.1 VSSIO IOB[15:0] 4.7 470K
VADREF VDDH(5V) 0.1 AVDD (3.3V) AVDD 100 2 0.1 VEXTREF 3 47
7. APPLICATION CIRCUITS
7.1. Application Circuit - (1)
SPY0029A
1
VDD (3.3V) 100 0.1
VDD IOA[6:0] VSS IOA[6:0]
SPCE061A Application Circuit (MIC_IN and with SPY0030A audio amplifier, for 3-battery use only)
Proprietary & Confidential
AVSS
V2VREF
(c) Sunplus Technology Co., Ltd.
16
Preliminary Version: 0.1
Preliminary
AUG. 02, 2002
3300p 3.3K 0.1 1K 3K 0.22 220 0.22 MIC 3K
10K 10K
SPCE061A
32768Hz
20p VDD
20p
VDDH(3.3V) RESET 87 0.1 RESET 100 0.1
4.7K
X32O
X32I
VCOIN
0.22 Speaker1 3 0.1 1K 1K MICP 6 4 1 2 DAC1 5 VMIC
0.1 VDDH(3.3V) SPY0030A 87 100 0.1
MICN
0.22 Speaker2 3 6 0.1 4 1K 1 2 5 0.1 DAC2 1K MICOUT 0.22
SPCE061A
OPI
5.1K
5000p
SPY0030A IOA[15:7] IOA[15:7] AGC IOB[15:0] VDDH(3.3V) VDDIO 100 0.1 VSSIO AVDD (3.3V) 0.1 AVDD VEXTREF 100 0.1 AVSS VDD (3.3V) VDD 100 0.1 IOA[6:0] VSS IOA[6:0] V2VREF 47 IOB[15:0] 4.7 470K
VADREF
7.2. Application Circuit - (2)
(c) Sunplus Technology Co., Ltd.
17
SPCE061A Application Circuit (MIC_IN and with SPY0030A audio amplifier, for 2-battery use only)
Proprietary & Confidential
Preliminary Version: 0.1
Preliminary
AUG. 02, 2002
20p 3300p VCOIN 3.3K 0.1 1K VMIC 3K 0.22 MICP 0.22 MICN 3K
10K 10K
SPCE061A
32768Hz
20p VDD X32O X32I
4.7K
VDDH(5V) 0.1 RESET
RESET
Speaker1
220 DAC1
VDDH(5V) 0.1 200~2K Speaker2
MIC
DAC2 0.1 MICOUT 200~2K 0.22
SPCE061A
OPI IOA[15:7] IOA[15:7]
5.1K
5000p
IOB[15:0]
IOB[15:0] AGC VDDH(5V) VDDIO 100 VDDH(5V) 0.1 VSSIO AVDD (3.3V) AVDD VADREF 0.1 100 2 0.1 47 4.7
470K
7.3. Application Circuit - (3)
SPY0029A
1
3
AVSS VDD VDD (3.3V) 100 0.1 IOA[6:0] VSS V2VREF
(c) Sunplus Technology Co., Ltd.
VEXTREF
18
IOA[6:0]
SPCE061A Application Circuit (MIC_IN and with BJT amplifier, for 3-battery use only)
Proprietary & Confidential
Preliminary Version: 0.1
Preliminary
AUG. 02, 2002
20p 3300p VCOIN 3.3K 0.1 1K VMIC 3K 0.22 MICP 0.22 MIC MICN 3K
10K 10K
SPCE061A
32768Hz
20p VDD X32O 4.7K RESET 0.1 RESET X32I
VDDH(3.3V)
Speaker1
220
DAC1 VDDH(3.3V) 0.1 200~2K Speaker2
DAC2 0.22 0.1 200~2K MICOUT
SPCE061A
OPI IOA[15:7] IOA[15:7] AGC IOB[15:0] IOB[15:0]
5.1K
5000p
4.7 VDDH(3.3V) VDDIO 100 0.1 VSSIO AVDD (3.3V) AVDD VEXTREF VADREF 0.1
470K
47
7.4. Application Circuit - (4)
AVSS VDD (3.3V) VDD 100 0.1
V2VREF
(c) Sunplus Technology Co., Ltd.
IOA[6:0] VSS IOA[6:0]
100
0.1
19
SPCE061A Application Circuit (MIC_IN and with BJT amplifier, for 2-battery use only)
Proprietary & Confidential
Preliminary Version: 0.1
Preliminary
AUG. 02, 2002
3300p 3.3K 0.1 VMIC
VEXTREF V2VREF
SPCE061A
32768Hz
20p VDD X32O X32I
20p
4.7K VDDH(3.3V) RESET 0.1 RESET VCOIN
Speaker1
DAC1 VDDH(3.3V) 0.1 200~2K Speaker2
MICP
MICN
Note: Case(1): Use AVDD(internal) as AD top reference voltage by setting P_ADC_CTRL($7015) b7 = 0 MICOUT DAC2
OPI 200~2K
SPCE061A
IOA[15:7] IOA[15:7] AGC
Case(2): Use V2VREF as AD top reference voltage by setting P_ADC_CTRL($7015) b7 = 1, b8 = 0
VEXTREF
IOB[15:0]
IOB[15:0] VADREF VDDH(3.3V) VDDIO 100 0.1 Note VSSIO AVDD (3.3V) AVDD VEXTREF 0.1
V2VREF
0.1F
100F
Case(3): Use external signal as AD top reference voltage by setting P_ADC_CTRL($7015) b7 =1, b8 = 1. (detail see the programming guide)
VEXTREF
7.5. Application Circuit - (5)
Input external signal as AD top reference voltage.
100
0.1 AVSS VDD (3.3V) VDD 100 0.1
V2VREF
V2VREF
(c) Sunplus Technology Co., Ltd.
IOA[6:0] VSS IOA[6:0] (7-channel LINE_IN)
20
0.1
SPCE061A Application Circuit (LINE_IN and with BJT amplifier, for 2-battery use only)
Proprietary & Confidential
Preliminary Version: 0.1
Preliminary
AUG. 02, 2002
3300p 3.3K 0.1 VMIC Note:
VEXTREF V2VREF
SPCE061A
32768Hz
20p VDD X32O X32I
20p
4.7K VDDH(3.3V) RESET 0.1 RESET VCOIN
Speaker1
DAC1 VDDH(3.3V) 0.1 200~2K Speaker2 MICN MICP
Case(1): Use AVDD(internal) as AD top reference voltage by setting P_ADC_CTRL($7015) b7 = 0
DAC2 0.1 200~2K
MICOUT
OPI
SPCE061A
IOA[15:7] IOA[15:7] AGC
Case(2): Use V2VREF as AD top reference voltage by setting P_ADC_CTRL($7015) b7 = 1, b8 = 0
VEXTREF
V2VREF
IOB[15:0]
IOB[15:0] VADREF VDDH(3.3V) VDDIO 100 0.1 Note VSSIO AVDD (3.3V) AVDD VEXTREF
VEXTREF
0.1F
100F
0.1
Case(3): Use external signal as AD top reference voltage by setting P_ADC_CTRL($7015) b7 =1, b8 = 1. (detail see the programming guide)
Input external signal as AD top reference voltage.
7.6. Application Circuit - (6)
100
0.1 AVSS VDD (3.3V) VDD 100 0.1
(c) Sunplus Technology Co., Ltd.
IOA[6:0] VSS IOA[6:0] (7-channel LINE_IN)
V2VREF
V2VREF
21
SPCE061A Application Circuit (LINE_IN and with BJT amplifier, for 2-battery use only)
Proprietary & Confidential
Preliminary Version: 0.1
Preliminary
SPCE061A
8. PACKAGE/PAD LOCATIONS
8.1. PAD Assignment
RESET VCOIN VSS VDDIO IOB10 IOB0 IOB1 IOB2 IOB3 IOB4 IOB5 IOB6 IOB7 IOB8 IOB9 VDD N/C
55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
X32O X32I TEST N/C VDD WDGOPT ICE ICECLK ICESDA VSS PVIN DAC1 DAC2 V2VREF AVSS AGC OPI MICOUT MICN PFUSE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
IOB11 IOB12 IOB13 IOB14 IOB15 SLEEP VSSIO ROMT IOA15 IOA14 IOA13 IOA12 IOA11 IOA10 IOA9
VEXTREF
VADREF
AVDD
MICP
VMIC
IOA0
IOA1
IOA2
IOA3
IOA4
IOA5
IOA6
IOA7
VSSIO
VSSIO
VDDIO
Chip Size: 3070m x 2970m This IC substrate should be connected to VSS
Note1: Chip size included scribe line. Note2: To ensure the IC functions properly, please bond all of VDD and VSS pins. Note3: The 0.1F capacitor between VDD and VSS should be placed to IC as closed as possible.
8.2. Ordering Information
Product Number SPCE061A-nnnnV-C
Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (V = A - Z).
Package Type Chip form
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22
VDDIO
IOA8
VSS
AUG. 02, 2002 Preliminary Version: 0.1
Preliminary
SPCE061A
8.3. PAD Locations
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PAD Name X32O X32I TEST N/C VDD WDGOPT ICE ICECLK ICESDA VSS PVIN DAC1 DAC2 V2VREF AVSS AGC OPI MICOUT MICN PFUSE MICP VADREF VEXTREF AVDD VMIC VSS IOA0 IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 VSSIO VSSIO X -1459.7 -1459.7 -1459.95 -1460.2 -1460.2 -1460.2 -1459.95 -1459.95 -1459.95 -1459.95 -1459.95 -1459.95 -1459.95 -1459.95 -1459.95 -1459.95 -1459.95 -1459.95 -1459.95 -1459.95 -1197.25 -1077.25 -957.25 -837.25 -717.25 -547.7 -427.7 -307.7 -187.7 -67.7 52.3 172.3 292.3 412.3 596.57 728.58 Y 1123.31 980.45 805.93 675.0 555.98 436.96 305.75 175.5 45.75 -84.25 -206.3 -326.3 -446.3 -565.9 -685.9 -805.9 -925.9 -1045.9 -1165.9 -1285.9 -1410 -1410 -1410 -1410 -1410 -1410 -1410 -1410 -1410 -1410 -1410 -1410 -1410 -1410 -1410 -1410 PAD No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 PAD Name VDDIO VDDIO IOA8 IOA9 IOA10 IOA11 IOA12 IOA13 IOA14 IOA15 ROMT VSSIO SLEEP IOB15 IOB14 IOB13 IOB12 IOB11 N/C VDDIO IOB10 IOB9 IOB8 IOB7 IOB6 IOB5 IOB4 IOB3 IOB2 IOB1 IOB0 X 859.58 1007.55 1137.55 1465.05 1465.05 1465.05 1465.05 1465.05 1465.05 1465.05 1465.05 1465.05 1465.05 1465.05 1465.05 1465.05 1465.05 1465.05 1461.2 1051.62 908.62 765.62 615.8 469.42 316.15 171.23 23.92 -125.5 -270.27 -417.22 -551.78 -707.33 -918.27 -1038.62 -1158.62 Y -1410 -1410 -1410 -1118.4 -994.7 -844.7 -694.7 -544.7 -394.7 -244.7 -94.7 55.3 205.3 355.3 505.3 655.3 805.3 955.3 1425 1415 1415 1415 1415 1415 1415 1415 1415 1415 1415 1415 1415 1415 1415 1415 1415
RESET
VDD VCOIN VSS
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AUG. 02, 2002 Preliminary Version: 0.1
Preliminary
SPCE061A
9. DISCLAIMER
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or FURTHER, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. publication are current before placing orders.
Accordingly, the reader is cautioned to verify that the data sheets and other information in this Products described herein are intended for use in normal commercial applications. Please note that application circuits
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. illustrated in this document are for reference purposes only.
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AUG. 02, 2002 Preliminary Version: 0.1
Preliminary
SPCE061A
10. REVISION HISTORY
Date AUG. 02, 2002 Revision # 0.1 Original Description Page 25
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AUG. 02, 2002 Preliminary Version: 0.1

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